In accordance with the well-known “Moore's law”, first formulated in 1965 [1], [2], integration density has doubled approximately every 18 months during the last 25 years. The related Technology Roadmap for Semiconductors (TRS) predicts, for microprocessors, that the number of transistors per chip will be about a billion in 2010 [3], [4].
The main reason of such a trend is an endless feature size reduction. In this scenario, the realization of electrical interconnections (contacts and vias), also referred to as interconnects, becomes more and more critical, and represents a limit to the scaling-down trend.
In particular, as circuit complexity increases (e.g., realization of complete systems on a chip or SOC), the number of interconnects also increases. The shrinking of transistor dimensions forces interconnect sizes to shrink as well (to fully exploit the increase in circuit density obtained with the feature size reduction). Moreover, for any chip, the electric performance depends on the behavior of all devices: transistors, capacitors, resistors, and interconnects as well.
Interconnects suffer from several possible types of failure. Most critical are the so-called “open-failures” at the contact and at the via level. An open-failure may signify a chip failure (this is generally the case of logic and memory chips). Of course, the larger the number of interconnects, the higher is the probability of having a chip failure due to interconnect failures.
Several phenomena can cause a failure across an interconnect, the most usual being a process fault (open-failure at time zero) and electromigration (failure during operation) [5]-[7]. The probability of both mechanisms of failure is inversely proportional to the size of contacts and vias. For the above reasons, in modern processing, manufacturing yield and circuit reliability become increasingly dependent on interconnects.
Of course, the basic requirements of interconnects are low resistance, stability during the fabrication process, and reliability during operation. Furthermore, interconnects (in particular, contacts and vias) must show a good adhesion to the underlying layer. So far, aluminium (or an aluminium-based alloy) has been the most used conductor to form interconnects in integrated silicon technology.
Aluminium (Al) processes have evolved to improve interconnect yield and reliability. The biggest problem in Al interconnects is represented by electromigration, which arises in the presence of an excessively high current density. At present, copper (Cu) is emerging as the leading conductor for interconnects due to its lower resistivity (1.7 μΩ·cm vs. 2.7 μΩ·cm) and its better immunity to electromigration.
In addition, the use of copper interconnects allows thinner and more closely spaced wires than Al-based technologies. Nevertheless, it must be pointed out that copper has several disadvantages. Above all, copper is more difficult to etch, thus requiring manufacturers to adopt new process steps. Moreover, it must be encapsulated with barrier materials for reliable integration with existing backend oxide dielectrics.
Several phenomena must be investigated to settle copper-based interconnect technology. For instance, in the presence of an electric field at temperatures as low as 150° C., positive Cu ions drift rapidly through silicon dioxide, thus degrading field isolation (by inducing dielectric leakage) and even active devices.
Furthermore, due to the continuous current density increase, electromigration and new process failures of vias and contacts represent a very critical issue. The dependence of these failures on the C/V aspect ratio must be analyzed. Some mechanisms for copper via failure have been reported [8]. One or more small voids can be present in the metallic copper that forms the via. The voids can join and migrate to the bottom of the via through either electromigration or, more critically, thermal-stress migration, thus opening the connection between the via and the barrier over the underlying metal layer. In some cases, thermal stress can be so great that the via metal tears away from the barrier material, thus forming a void and opening the connection.
A further possible drawback in scaled-down devices is represented by the leakage current between adjacent metal lines (belonging either to the same level or to different levels). As mentioned above, the use of copper can lead to oxide contamination. The ensuing leakage current can both contribute to increase the power consumption and decrease manufacturing yield. This aspect also needs also to be experimentally analyzed.
For the above reasons, to improve the performance of interconnects (to be more specific, of contacts and vias) it is fundamentally mandatory to use a test chip able to experimentally evaluate their behavior. Moreover, because of the many metal layers that are used in modern processes, the test system should be able to detect open-failures between any pair of adjacent metal levels of the test chip. Indeed, it would be desirable to obtain the statistical failure distribution for any different via level, so as to be able to improve the manufacturing process at every step.
Due to the statistical nature of failures, a large amount of experimental data is needed. The time to perform all the necessary measurements should be kept as low as possible. The above requirements represent a key design constraint for any suitable test device [9], [10]. Furthermore, to reduce testing time and cost, it would be desirable to have a test chip that allows all the above measurements. To improve the fabrication process, a detailed physical analysis of the detected failures must eventually be carried out. Because the number of failures is relatively small, the location of any failed element should be exactly determined.